TinyTinyTPU: 2×2 systolic-array TPU-style matrix-multiply unit deployed on FPGA

Summary

TinyTinyTPU A minimal 2×2 systolic-array TPU-style matrix-multiply unit, implemented in SystemVerilog and deployed on FPGA. This project implements a complete TPU architecture including: 2×2 systolic array (4 processing elements) Full post-MAC pipeline (accumulator, activation, normalization, quantization) UART-based host interface Multi-layer MLP inference capability FPGA deployment on Basys3 (Xilinx Artix-7) Resource Usage (Basys3 XC7A35T): LUTs: ~1,000 (5% utilization) Flip-Flops: ~1,000 (3% utilization) DSP48E1: 8 slices BRAM: ~10-15 blocks Estimated Gate Count: ~25,000 gates Table of Contents Project Overview TinyTinyTPU is an educational implementation of Google's TPU architecture, scaled down to a 2×2 systolic array. It demonstrates: Systolic Array Architecture : Data flows horizontally (activations) and vertically (partial sums) : Data flows horizontally (activations) and vertically (partial sums) Diagonal Wavefront Weight Loading : Staggered weight capture for proper systolic timing : Staggered weight capture for proper systolic timing Full MLP Pipeline : Weight FIFO → MMU → Accumulator → Activation → Normalization → Quantization : Weight FIFO → MMU → Accumulator → Activation → Normalization → Quantization Multi-Layer Inference: Supports sequential layer processing with double-buffered activations Design Philosophy This is a minimal, educational-scale TPU designed for: Learning TPU architecture principles Understanding systolic array dataflow FPGA prototyping and experimentation Small-scale ML inference (2×2 matrices) For production workloads, scale up the array size (e.g., 256×256 like Google TPU v1). Quick Start Prerequisites For Simulation: Verilator 5.022 or later Python 3.8+ cocotb GTKWave or Surfer (for waveform viewing) For FPGA Build: Xilinx Vivado 2020.1 or later (for Basys3) OR Yosys + nextpnr (open source alternative, see Open Source Tooling) For Running Inference: Basys3 FPGA board USB cable for programming Python 3.8+ with pyserial Installation...